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| LTC1041 BANG-BANG Controller FEATURES s s s DESCRIPTIO s s s s Micropower 1.5W (1 Sample/Second) Wide Supply Range 2.8V to 16V High Accuracy Guaranteed SET POINT Error 0.5mV Max Guaranteed Deadband 0.1% of Value Max Wide Input Voltage Range V + to Ground TTL Outputs with 5V Supply Two Independent Ground-Referred Control Inputs Small Size 8-Pin SO APPLICATIO S s s s s The LTC(R)1041 is a monolithic CMOS BANG-BANG controller manufactured using Linear Technology's enhanced LTCMOSTM silicon gate process. BANG-BANG loops are characterized by turning the control element fully ON or fully OFF to regulate the average value of the parameter to be controlled. The SET POINT input determines the average control value and the DELTA input sets the deadband. The deadband is always 2 x DELTA and is centered around the SET POINT. Independent control of the SET POINT and deadband, with no interaction, is made possible by the unique sampling input structure of the LTC1041. An external RC connected to the OSC pin sets the sampling rate. At the start of each sample, internal power to the analog section is switched on for 80s. During this time, the analog inputs are sampled and compared. After the comparison is complete, power is switched off. This achieves extremely low average power consumption at low sampling rates. CMOS logic holds the output continuously while consuming virtually no power. To keep system power at an absolute minimum, a switched power output (VP-P) is provided. External loads, such as bridge networks and resistive dividers, can be driven by this switched output. The output logic sense (i.e., ON = V+) can be reversed (i.e., ON = GND) by interchanging the VIN and SET POINT inputs. This has no other effect on the operation of the LTC1041. Temperature Control (Thermostats) Motor Speed Control Battery Charger Any ON-OFF Control Loop , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO 26V AC 2-WIRE THERMOSTAT 56 0.1F 4.32k 4.99k Supply Current vs Sampling Frequency 10000 1000 1 2 8 7 LTC1041 6 5 1F DELTA = 0.5F 10M IS 400nA Ultralow Power 50F to 100F (2.4W) Thermostat VS = 6V SUPPLY CURRENT, IS (A) 100 10 1 0.1 5k 2N6660 1N4002 (4) 49.9 3 4 6.81k + 6V LTC1041 * TA01 ALL RESISTORS 1%. YELLOW SPRINGS INSTRUMENT CO., INC. P/N 44007. DRIVING THERMISTOR WITH VP-P ELIMINATES 3.8F ERROR DUE TO SELF-HEATING 0.01 0.1 1 10 100 1000 SAMPLING FREQUENCY, fS (Hz) 10000 LTC1041 * TA02 U TOTAL SUPPLY CURRENT LTC1041 SUPPLY CURRENT 1041fa U U 1 LTC1041 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW ON / OFF VIN SET POINT GND 1 2 3 4 8 7 6 5 V+ VP-P OSC DELTA Total Supply Voltage (V + to V -) .............................. 18V Input Voltage ........................ (V + + 0.3V) to (V - - 0.3V) Operating Temperature Range LTC1041C ......................................... -40C to 85C LTC1041M (OBSOLETE) .................. - 55C to125C Storage Temperature Range ................. - 55C to 150C Lead Temperature (Soldering, 10 sec).................. 300C Output Short Circuit Duration ....................... Continuous ORDER PART NUMBER LTC1041CN8 LTC1041CS8 N8 PACKAGE S8 PACKAGE 8-LEAD PDIP 8-LEAD PDIP TJMAX = 110C, JA = 150C/W (N8) TJMAX = 150C, JA = 150C/W (S8) J8 PACKAGE 8-LEAD CERDIP TJMAX = 150C, JA = 100C/W LTC1041MJ8 OBSOLETE PACKAGE Consider the N8 Package as an Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER SET POINT Error (Note 3) The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test Conditions: V+ = 5V, unless otherwise specified. CONDITIONS V + = 2.8V to 6V (Note 2) q MIN V + = 6V to 15V (Note 2) q Deadband Error (Note 4) V + = 2.8V to 6V (Note 2) q V + = 6V to 15V (Note 2) q IOS RIN PSR IS(ON) IS(OFF) tD VOH VOL REXT fS Input Current Equivalent Input Resistance Input Voltage Range Power Supply Range Power Supply ON Current (Note 6) Power Supply OFF Current (Note 6) Response Time (Note 7) ON/OFF Output (Note 8) Logical "1" Output Voltage Logical "0" Output Voltage External Timing Resistor Sampling Frequency A = 25C, OSC = GND (VIN, SET POINT and DELTA Inputs) fS = 1kHz (Note 5) V + = 5V, T TC1041M/LTC1041C TYP 0.3 + 0.05 1 + 0.05 0.6 + 0.1 2 + 0.1 0.3 15 MAX 0.5 + 0.1 3 + 0.1 1 + 0.2 6 + 0.2 UNITS mV % of DELTA mV % of DELTA mV % of DELTA % of DELTA nA M V V mA A A s V V k Hz q q q 10 GND 2.8 V+ 1.2 0.001 0.001 80 4.4 0.25 5 16 3 0.5 5 100 V + = 5V, VP-P ON V + = 5V, VP-P OFF V + = 5V V + = 4.75V, IOUT = -360A V + = 4.75V, IOUT = 1.6mA Resistor Connected between V+ and OSC Pin V + = 5V, TA = 25C, REXT = 1M CEXT = 0.1F LTC1041C LTC1041M q q q 60 q q 2.4 100 0.4 10,000 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Applies over input voltage range limit and includes gain uncertainty. 1041fa 2 U W U U WW W LTC1041 ELECTRICAL CHARACTERISTICS Note 3: SET POINT error + ( VU 2 VL ) - SET POINT where VU = upper band limit and VL = lower band limit. Note 4: Deadband error (VU - VL) - 2 * DELTA where VU = upper band limit and VL = lower band limit. Note 5: RIN is guaranteed by design and is not tested. RIN = 1/(fS x 66pF). Note 6: Average supply current = tD * IS(ON) * fS + (1 - tD * fS) lS(OFF). Note 7: Response time is set by an internal oscillator and is independent of overdrive voltage. tD = VP-P pulse width. Note 8: Output also capable of meeting EIA/JEDEC standard B series CMOS drive specifications. TYPICAL PERFOR A CE CHARACTERISTICS IS(ON) vs V+ 20 2.2 NORMALIZED SAMPLING FREQUENCY (fS AT 5V, 25C) 18 16 14 TA = 125C 1.6 1.4 1.2 1.0 0.8 TA = - 55C 0.6 0 2 8 10 12 4 6 SUPPLY VOLTAGE, V+ (V) 14 16 TA = 25C IS(ON) (mA) 12 10 8 6 4 2 0 2 4 10 8 6 12 SUPPLY VOLTAGE, V+ (V) 125C -55C 25C SAMPLE RATE, fS (Hz) Response Time vs Supply Voltage 300 250 RESPONSE TIME, tD (s) TA = 25C 200 150 100 50 0 2 4 10 14 8 12 6 SUPPLY VOLTAGE, V+ (V) 16 RESPONSE TIME, t D (s) UW 14 16 LTC1041 * TPC01 Normalized Sampling Frequency vs V +, Temperature R = 1M, C = 0.1F 103 Sampling Rate vs REXT, CEXT CEXT = 1000pF 2.0 1.8 102 CEXT = 0.01F 10 CEXT = 0.05F CEXT = 0.1F 1 CEXT = 1F 0.1 100k 1M REXT () 10M LTC1041 * TPC03 LTC1041 * TPC02 Response Time vs Temperature 130 120 110 100 90 80 70 60 50 40 -50 0 25 -25 75 100 50 AMBIENT TEMPERATURE, TA (C) 125 V+ = 5V LTC1041 * TPC04 LTC1041 * TPC05 1041fa 3 LTC1041 TYPICAL PERFOR A CE CHARACTERISTICS VP-P Output Voltage vs Load Current AVERAGE INPUT RESISTANCE, RIN (1/fS * 66pF) () TYPICAL OUTPUT VOLTAGE DROP (V+ - VP-P) (V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1 2 345678 LOAD CURRENT, IL (mA) 9 10 V+ = 2.8V V+ = 16V V+ = 10V APPLICATIO S I FOR ATIO The LTC1041 uses sampled data techniques to achieve its unique characteristics. It consists of two comparators, each of which has two differential inputs (Figure 1a). When the sum of the voltages on a comparator's inputs is positive, the output is high and when the sum is negative, the output is low. The inputs are interconnected such that V+ (8) COMP A 4 ON/OFF (1) VIN (2) + - + - ON/OFF OUTPUT SET POINT (3) DELTA (5) GND (4) OSC (6) CEXT + - + - COMP B V+ 4 REXT V+ VP-P CIRCUIT VP-P (7) TIMING GENERATOR POWER ON 80s (a) Figure 1. LTC1041 Block Diagram 4 U W UW RIN vs Sampling Frequency 10 11 1010 109 V+ = 5V 108 107 1 10 102 103 SAMPLING FREQUENCY fS (Hz) 104 LTC1041 * TPC06 LTC1041 * TPC07 UU the R S flip-flop is reset (ON/OFF = GND) when VIN > (SET POINT + DELTA) and is set (ON/OFF = V+) when VIN < (SET POINT - DELTA). This makes a very precise hysteresis loop of 2 * DELTA centered around the SET POINT. (See Figure 1b.) For RS < 10k The dual differential input structure is made with CMOS switches and a precision capacitor array. Input impedance characteristics of the LTC1041 can be determined from the equivalent circuit shown in Figure 2. The input capacitance will charge with a time constant of SET POINT DELTA - + DELTA V+ DEADBAND GND 0V VL INPUT VOLTAGE, VIN VU LTC1041 * AI01b LTC1041 * AI01a (b) 1041fa LTC1041 APPLICATIO S I FOR ATIO RS VIN CS S1 CIN ( 33pF) + S2 - V- LTC1041 DIFFERENTIAL INPUT LTC1041 * AI01 Figure 2. Equivalent Input Circuit RS * CIN. The ability to fully charge CIN from the signal source during the controller's active time is critical in determining errors caused by the input charging current. For source resistances less than 10k, CIN fully charges and no error is caused by the charging current. For RS > 10k For source resistances greater than 10k, CIN cannot fully charge, causing voltage errors. To minimize these errors, an input bypass capacitor, CS, should be used. Charge is shared between CIN and CS, causing a small voltage error. The magnitude of this error is AV = VIN * CIN (CIN + CS). This error can be made arbitrarily small by increasing CS. The averaging effect of the bypass capacitor, CS, causes another error term. Each time the input switches cycle between the plus and minus inputs, CIN is charged and discharged. The average input current due to this is IAVG = VIN * CIN * fS, where fS is the sampling frequency. Because the input current is directly proportional to the differential input voltage, the LTC1041 can be said to have an average input resistance of RIN = VIN/IAVG = I/(fS * CIN). Since two comparator inputs are connected in parallel, RIN is one half of this value (see typical curve of RIN versus Sampling Frequency). This finite input resistance causes an error due to the voltage divider between RS and RIN. The input voltage error caused by both of these effects is VERROR = VIN [2CIN/(2CIN + CS) + RS/(RS + RIN)]. Example: assume fS = 10Hz, RS = 1M, CS = 1F, VIN = 1V, VERROR = 1V(66V + 660V) = 726V. Notice that most of the error is caused by RIN. If the sampling frequency is reduced to 1Hz, the voltage error from the input impedance effects is reduced to 136V. U Input Voltage Range The input switches of the LTC1041 are capable of switching either to the V+ supply or ground. Consequently, the input voltage range includes both supply rails. This is a further benefit of the sampling input structure. Error Specifications The only measurable errors on the LTC1041 are the deviations from "ideal" of the upper and lower switching levels (Figure 1b). From a control standpoint, the error in the SET POINT and deadband is critical. These errors may be defined in terms of VU and VL. V +V SET POINT error U L - SET POINT 2 deadband error ( VU - VL ) - 2 * DELTA W UU The specified error limits (see electrical characteristics) include error due to offset, power supply variation, gain, time and temperature. Pulsed Power (VP-P) Output It is often desirable to use the LTC1041 with resistive networks such as bridges and voltage dividers. The power consumed by these resistive networks can far exceed that of the LTC1041 itself. At low sample rates the LTC1041 spends most of its time off. A switched power output, VP-P, is provided to drive the input network, reducing its average power as well. VP-P is switched to V+ during the controller's active time ( 80s) and to a high impedance (open circuit) when internal power is switched off. Figure 3 shows the VP-P output circuit. The VP-P output voltage is not precisely controlled when driving a load (see typical curve of VP-P Output Voltage vs Load Current). In spite of this, high precision can be achieved in two ways: (1) driving ratiometric networks and (2) driving fast settling references. In ratiometric networks all the inputs are proportional to VP-P (Figure 4). Consequently, the absolute value of VP-P does not affect accuracy. 1041fa 5 LTC1041 APPLICATIO S I FOR ATIO V+ 8 Q1 80s COMPARATOR ON TIME 4 GND P1 7 VP-P LTC1041 * AI03 Figure 3. VP-P Output Switch R1 R3 R4 R2 R5 R6 1 VIN 2 SET POINT 3 GND 4 LTC1041 Figure 4. Ratiometric Network Driven by VP-P R1 1 IL R2 VIN SET POINT 3 4 2 LTC1041 8 7 6 R3 LT1009-2.5 R4 5 DELTA LTC1041 * AI05 Figure 5. Driving Reference with VP-P Output If the best possible performance is needed, the inputs to the LTC1041 must completely settle within 4s of the start of the comparison cycle (VP-P high impedance to V + transition). Also, it is critical that the input voltages do not change during the 80s active time. When driving resistive input networks with VP-P, capacitive loading should be minimized to meet the 4s settling time requirement. Further, care should be exercised in layout when driving networks with source impedances, as seen by the LTC1041, of greater than 10k (see For RS > 10k). 6 U In applications where an absolute reference is required, the VP-P output can be used to drive a fast settling reference. The LTC1009 2.5V reference settles in 2s and is ideal for this application (Figure 5). The current through R1 must be large enough to supply the LT1009 minimum bias current ( 1mA) and the load current, IL. Internal Oscillator An internal oscillator allows the LTC1041 to strobe itself. The frequency of the oscillation, and hence the sampling rate, is set with an external RC network (see typical curve, Sampling Rate REXT, CEXT). REXT and CEXT are connected as shown in Figure 1. To assure oscillation, REXT must be between 100k and 10M. There is no limit to the size of CEXT. At low sampling rates, REXT is very important in determining the power consumption. REXT consumes power continuously. The average voltage at the OSC pin is approximately V+/2, giving a power dissipation of PREXT = (V+/ 2)2/REXT. Example: assume REXT = 1M, V+ = 5V, PREXT = (2.5)2/106 = 6.25/W. This is approximately four times the power consumed by the LTC1041 at V+ = 5V and fS = 1 sample/second. Where power is a premium, REXT should be made as large as possible. Note that the power dissipated by REXT is not a function of fS or CEXT. If high sampling rates are needed and power consumption is of secondary importance, a convenient way to get the maximum possible sampling rate is to make REXT = 100k and CEXT = 0. The sampling rate, set by the controller's active time, will nominally be 10kHz. To synchronize the Sampling of the LTC1041 to an external frequency source, the OSC pin can be driven by a CMOS gate. A CMOS gate is necessary because the input trip points of the oscillator are close to the supply rails and TTL does not have enough output swing. Externally driven, there will be a delay from the rising edge of the OSC input and the start of the sampling cycle of approximately 5s. V+ 8 7 VP-P 6 5 DELTA LTC1041 * AI04 W UU V+ 1041fa LTC1041 TYPICAL APPLICATIO S Motor Speed Controller V+ 100k 10k 1N4002 MOTOR* TACH V+ 1.1k 2N6387 1 2 3 4 LTC1041 8 7 6 5 320pF LT1009 320k 24k 3k SPEED DEMAND 20k *CANNON CKT26-T5-3SAE GE 106B 74C00 UTC D0T20 V+ 12V LEAD ACID 2k 36.5k 40k 1 2 3 4 2.21k 10k LTC1041 8 7 6 5 0.1F 1N4022 74C00 1N4002 13 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 500 DEADBAND LTC1041 * TA03 Battery Charger 89 OUT LT1019-5 IN 5V 74C00 + 1N4002 24V 1A 115VAC 60 Hz 100F 100k SCR FIRES AT ZERO CROSSING. * SET BATTERY VOLTAGE. BATTERY IS MEASURED WITH ZERO CHARGE CURRENT LTC1041 * TA04 1041fa 7 LTC1041 PACKAGE DESCRIPTIO CORNER LEADS OPTION (4 PLCS) .300 BSC (7.62 BSC) .023 - .045 (0.584 - 1.143) HALF LEAD OPTION .045 - .068 (1.143 - 1.650) FULL LEAD OPTION .045 - .065 (1.143 - 1.651) .014 - .026 (0.360 - 0.660) .100 (2.54) BSC .200 (5.080) MAX .015 - .060 (0.381 - 1.524) .008 - .018 (0.203 - 0.457) 0 - 15 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .300 - .325 (7.620 - 8.255) .008 - .015 (0.203 - 0.381) .065 (1.651) TYP .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076) ( +.035 .325 -.015 +0.889 8.255 -0.381 ) INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) NOTE: 1. DIMENSIONS ARE .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) .053 - .069 (1.346 - 1.752) 0- 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .014 - .019 (0.355 - 0.483) TYP 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) .005 (0.127) MIN .405 (10.287) MAX 8 7 6 5 .025 (0.635) RAD TYP 1 .125 3.175 MIN 2 3 .220 - .310 (5.588 - 7.874) 4 J8 0801 OBSOLETE PACKAGE N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 .045 - .065 (1.143 - 1.651) .130 .005 (3.302 0.127) .255 .015* (6.477 0.381) 1 2 3 4 N8 1002 .100 (2.54) BSC S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 - .197 (4.801 - 5.004) NOTE 3 8 .004 - .010 (0.101 - 0.254) .228 - .244 (5.791 - 6.197) N/2 1 .030 .005 TYP 2 3 N/2 7 6 5 N N .150 - .157 (3.810 - 3.988) NOTE 3 .245 MIN .160 .005 .050 BSC .045 .005 .050 (1.270) BSC 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT SO8 0502 1041fa LW/TP 1202 1K REV A * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 1985 |
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